An infrastructure for debug using clusters of assertion-checkers
Microelectronics and reliability
Available online xxxx a b s t r a c t It has become indispensable to locate circuit defects and find the root-cause of errors as soon as the prototype of a system (first-silicon) gets ready. Various Design-for-Debug (DfD) solutions have been introduced as a means to increase the observability and controllability of internal signals, resulting to a speed-up in debugging process and a decrease in the time-to-market of new products. Assertion Based Verification (ABV) is one of the instrumental
... silicon verification techniques. Once assertions are converted to hardware modules and incorporated into a debug infrastructure, the post-silicon debug can benefit from the additional observability provided by such assertions. In this paper, we first propose a new algorithm that generates clusters of assertion-checkers; in our proposed clustering algorithm, we resort to a graph partitioning algorithm to find the assertion-checkers that can be placed inside a cluster. The proposed method generates the clusters of assertion-checkers by means of exploring the logic-cones set of each assertion-checker. Moreover, coverage metrics for different configurations of clusters are defined. Then, we introduce several mechanisms through which the clusters of assertion-checkers can be incorporated into the DfD infrastructures. In our experiments, several case studies such as AXI bus, PCI bus protocol and a memory controller are considered; thereafter, the proposed debug infrastructure containing clusters of assertion-checkers is embedded into such case studies. It turns out that contrary to a non-clustering approach of placing assertion-checkers into a design the clustering algorithm along with the proposed method for incorporating assertion-checker clusters into a debug infrastructure lead to the better results in terms of the energy consumption and design coverage.