Ultra low-cost defect protection for microprocessor pipelines

Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd Austin
2006 SIGARCH Computer Architecture News  
The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Silicon failure mechanisms, such as transistor wearout and manufacturing defects, are a growing challenge that threatens the yield and product lifetime of future systems. In this paper we introduce the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system
more » ... om silicon defects. To achieve this goal we combine area-frugal on-line testing techniques and system-level checkpointing to provide the same guarantees of reliability found in traditional solutions, but at much lower cost. Our approach utilizes a microarchitectural checkpointing mechanism which creates coarse-grained epochs of execution, during which distributed on-line built in self-test (BIST) mechanisms validate the integrity of the underlying hardware. In case a failure is detected, we rely on the natural redundancy of instructionlevel parallel processors to repair the system so that it can still operate in a degraded performance mode. Using detailed circuit-level and architectural simulation, we find that our approach provides very high coverage of silicon defects (89%) with little area cost (5.8%). In addition, when a defect occurs, the subsequent degraded mode of operation was found to have only moderate performance impacts, (from 4% to 18% slowdown). of more robust devices, component yield and lifetime will soon be compromised. In this paper, we introduce a low-cost mechanism for tolerating a small number of silicon failures that occur in the field, i.e., while the device is in operation.
doi:10.1145/1168919.1168868 fatcat:735im5zajzbpxcsyijynplvdwq