I-cache multi-banking and vertical interleaving

Sangyeun Cho
2007 Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07  
This research investigates the impact of a microarchitectural technique called vertical interleaving in multi-banked caches. Unlike previous multi-banking and interleaving techniques to increase cache bandwidth, the proposed vertical interleaving further divides memory banks in a cache into vertically arranged sub-banks, which are selectively accessed based on the memory address. Under this setting, we are particularly interested in how accesses to instruction cache are dispersed toward
more » ... t cache banks. We quantitatively analyze the memory access pattern seen by each cache bank and establish the relationship between important cache parameters and the access patterns. Our study shows that the vertical interleaving technique distributes accesses among different banks with tightly bounded run lengths. We then discuss possible applications that utilize the presented concept, including power density reduction. Very simple interleaving configurations can lead to as much as 67% reduction of maximum power density under a realistic machine configuration. Our study suggests that the idea of vertically interleaving cache lines has potential for optimizing memory accesses in a number of interesting ways.
doi:10.1145/1228784.1228794 dblp:conf/glvlsi/Cho07 fatcat:d7mbnjscarepxanuvq7rdunwxa