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This research investigates the impact of a microarchitectural technique called vertical interleaving in multi-banked caches. Unlike previous multi-banking and interleaving techniques to increase cache bandwidth, the proposed vertical interleaving further divides memory banks in a cache into vertically arranged sub-banks, which are selectively accessed based on the memory address. Under this setting, we are particularly interested in how accesses to instruction cache are dispersed towarddoi:10.1145/1228784.1228794 dblp:conf/glvlsi/Cho07 fatcat:d7mbnjscarepxanuvq7rdunwxa