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Technology mapping algorithms for hybrid fpgas containing lookup tables and plas
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Programmable devices containing lookup tables (LUTs) and programmable logic arrays (PLAs) provide a heterogeneous target platform for user designs. Present commercial tools, which target these hybrid devices, require hand partitioning of user designs to isolate logic for each type of logic resource. In this paper, an automated technology mapping tool, hybridmap, is presented that identifies design logic partitions as suitable for either LUT or PLA implementation. A breadth-first search-baseddoi:10.1109/tcad.2003.810743 fatcat:vp4jmm4pzresfj7gtmvysfshj4