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Chip Multiprocessor Traffic Models Providing Consistent Multicast and Spatial Distributions
2008
Simulation (San Diego, Calif.)
Chip multiprocessors (CMPs) have become the center of attention in recent years. They consist of multiple processor cores on a single chip. These cores are connected on-chip by a bus or, if many cores are involved, by an appropriate network. To investigate how a multicore processor behaves dependent on the chosen network-on-chip topology, a corresponding model must be established for performance evaluation. Modeling and simulating the entire system would lead to high model complexity. Thus, it
doi:10.1177/0037549708091638
fatcat:opux7kwufbcwra6wgd2qh6ewcm