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Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local layout density. To improve manufacturability and performance predictability, area fill features are inserted into the layout to improve uniformity with respect to density criteria. However, the performance impact of area fill insertion is not considered by any fill method in the literature. In this paper, we firstdoi:10.1109/dac.2003.1218772 fatcat:mphcwyuy6jh6ncpw25of6lmqlq