A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf
.
Improving software pipelining with hardware support for self-spatial loads
1999
SIGARCH Computer Architecture News
Recent work in software pipelining in the presence of uncertain memory latencies has shown that using compilergenerated cache-reuse analysis to determine proper load latencies can improve performance significantly [14, 19, 9] . Even with reuse information, references with a stride-one access pattern in the cache (called self-spatial loads) have been treated as all cache hits or all cache misses rather than as a single cache miss followed by a few cache hits in the rest of the cache line. In
doi:10.1145/309758.309784
fatcat:icxaotwhbnbu7i6lfb65ubr3em