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Towards a Generic Verification Methodology for System Models
2013
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
The use of modeling languages such as UML or SysML enables to formally specify and verify the behavior of digital systems already in the absence of a specific implementation. However, for each modeling method and verification task usually a separate verification solution has to be applied today. In this paper, a methodology is envisioned that aims at stopping this "inflation" of different verification approaches and instead employs a generic methodology. For this purpose, a given specification
doi:10.7873/date.2013.248
dblp:conf/date/WilleGSKD13
fatcat:4rhmxydwdvh2hb4jmj2bgwh4kq