Towards a Generic Verification Methodology for System Models

Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013  
The use of modeling languages such as UML or SysML enables to formally specify and verify the behavior of digital systems already in the absence of a specific implementation. However, for each modeling method and verification task usually a separate verification solution has to be applied today. In this paper, a methodology is envisioned that aims at stopping this "inflation" of different verification approaches and instead employs a generic methodology. For this purpose, a given specification
more » ... s well as the verification shall be transformed into a basic model which itself is specified by means of a generic modeling language. Then, a range of automatic reasoning engines shall uniformly be applied to perform the actual verification. A feasibility study demonstrates the applicability of the envisioned approach.
doi:10.7873/date.2013.248 dblp:conf/date/WilleGSKD13 fatcat:4rhmxydwdvh2hb4jmj2bgwh4kq