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Simulation and Analysis of 6T SRAM Cell using Power Reduction Techniques
2012
IOSR Journal of Engineering
The demand for static random-access memory (SRAM) is increasing with large use of SRAM in System On-Chip and high-performance VLSI circuits. The high-density VLSI circuits and the exponential dependency of the leakage current on the oxide thickness is becoming a major challenge in deep-sub-micron CMOS technology. As the density of SRAM increases, the leakage power has become a significant component in chip design. This paper represents the simulation of 6T SRAM cells using low power reduction
doi:10.9790/3021-021145149
fatcat:pctjudb5tvdl7gka32b6tclh44