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Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study
2012
2012 15th Euromicro Conference on Digital System Design
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In this paper, we present a method for the design of MPSoCs for complex data-intensive applications. This method aims at a blend exploration of the communication, the memory system architecture and the computation resource parallelism. The proposed method is exemplified on a JPEG Encoder case study by describing all the design steps. Our method allows for a JPEG encoder implementation having a throughput increase of 84% and an increase of the achievable FPGA maximum frequency fmax of 64% with
doi:10.1109/dsd.2012.133
dblp:conf/dsd/CorvinoDGJ12
fatcat:q4f2algbm5ampoaafcdhhtz4dm