Most of the microelectronics components developed for the first generation of LHC experiments have been defined and designed with very precise experiment specific goals and are hardly adaptable to other applications. In an effort to cover the needs for generic programmable components, often needed in the real world, an industry-compatible Programmable Logic Device (PLD) and an industry-compatible Field-Programmable Gate Array (FPGA) are now under development. This effort is targeted to small

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... ume applications or to the cases where small programmable functions are required to fix a system application. The PLD is a fuse-based, 10-input, 8-I/O general architecture device compatible with a popular commercial part, in 0.25 µm CMOS. The FPGA under development is instead a 32 × 32 logic block array, equivalent to ≈ 25k gates, in 0.13 µm CMOS. SEU-robust registers are employed for configuration registers as well as for user data flip-flops.