Low power design using double edge triggered flip-flops

R. Hossain, L.D. Wronski, A. Albicki
1994 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Abstruct-In this paper we study the power savings possible using double edge triggered (DET), instead of, conventional single edge triggered (SET) flip-flops. We begin the paper by introducing a set of novel D-type double edge triggered flip-flops which can be implemented with fewer transistors than any previous design. The power dissipation in these flipflops and single edge triggered flip-flops is compared via architectural level studies, analytical considerations and simulations. The
more » ... includes an implementation independent study on, the effect of input sequences, in the energy dissipation of single and double edge triggered flip-flops. The system level energy savings possible by using registers consisting of double edge triggered flip-flops, instead of single edge triggered flip-flops, is subsequently explored. The results are extremely encouraging, indicating that double edge triggered flip-flops are capable of significant energy savings, for only a small overhead in complexity.
doi:10.1109/92.285754 fatcat:sjw4d25sdvdvfbnrrl4xenym2u