A 1–190MSample/s 8–64 tap energy-efficient reconfigurable FIR filter for multi-mode wireless communication

Farhana Sheikh, Melinda Mill, Brian Richards, Dejan Markovic, Borivoje Nikolic
2010 2010 Symposium on VLSI Circuits  
An energy-efficient reconfigurable distributed-arithmetic FIR filter for multi-mode wireless communication is fabricated in 7M1P 90nm CMOS and occupies 1.5mm 2 . A 6way parallel, 2-way time-multiplexed architecture with circuits for memory offset binary coding and memory partitioning enable input wordlength and tap configurability with 1-190MSample/s throughput and 10-130mW total power measured at 1.1V, 25°C.
doi:10.1109/vlsic.2010.5560297 fatcat:aijqb5etnrcvdlde3b24a5fmoq