Clock Buffer Polarity Assignment for Power Noise Reduction

Rupak Samanta, Ganesh Venkataraman, Jiang Hu
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assignment algorithms are proposed: 1) partitioning; 2) 2-coloring on minimum spanning tree; and 3) recursive minmatching. A post-processing of clock buffer sizing is performed to achieve desired clock skew. SPICE based experimental results
more » ... ental results indicate that our techniques could reduce the average peak current and average delay variations by 50% and 51%, respectively. Index Terms-Clock distribution, clock skew, polarity, power/ ground noise. I. INTRODUCTION W HEN the supply voltage decreases with VLSI technology scaling, circuit performance becomes increasingly vulnerable to power/ground noise [1]- [3] . This problem is exacerbated by the increase in frequency and and large gate count in the scaled technologies. Based on an estimation in [4], a 0.1-V power noise may cause 80% inverter delay variation at 45-nm technology. A main culprit of power noise is clock network which keeps drawing huge current frequently from the power supply network [5]- [9] . Power/ground noise is acute at the beginning of clock cycle when FFs and the gates are switching simultaneously. In order to reduce the clock-induced power noise, few works [5]-[7], [9] attempt to avoid simultaneous flip-flop switchings through clock skew scheduling. The common approach is to spread the computation across the entire clock period so that the peak of the power/ground noise occurring at the beginning of the clock cycle is distributed across the entire clock period. In [5], [6], the flip-flops are grouped into buckets that are switched at different times. However, such an approach suffers from the limitation that the flip-flops within the same bucket still switch at the same instant of time. Moreover, the approaches [5], [6], do not consider the effect of clock skew scheduling on current profiles of combinational logic. The work [7], uses a graph based clock scheduling approach
doi:10.1109/iccad.2006.320174 fatcat:ioigkcs6qbhvzm7rulqbqiasou