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High-Level Design Optimizations for Implementing Data Stream Sketch Frequency Estimators on FPGAs
2022
Electronics
This paper presents simple yet effective optimizations for implementing data stream frequency estimation sketch kernels using High-Level Synthesis (HLS). The paper addresses design issues common to sketches utilizing large portions of the embedded RAM resources in a Field Programmable Gate Array (FPGA). First, a solution based on Load-Store Queue (LSQ) architecture is proposed for resolving the memory dependencies associated with the hash tables in a frequency estimation sketch. Second,
doi:10.3390/electronics11152399
fatcat:bir4w3e6h5gjfjwf5jbs3fraoi