A physical design study of fabscalar-generated superscalar cores

Niket K. Choudhary, Brandon H. Dwiel, Eric Rotenberg
2012 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)  
FabScalar is a recently published tool for automatically generating superscalar cores, of different pipeline widths, depths and sizes. The output of FabScalar is a synthesizable register-transfer-level (RTL) description of the desired core. While this capability makes sophisticated cores more accessible to designers and researchers, meaningful applications require reducing RTL descriptions to physical designs. This paper presents the first systematic physical design study of FabScalargenerated superscalar cores.
doi:10.1109/vlsi-soc.2012.6379024 dblp:conf/vlsi/ChoudharyDR12 fatcat:bivkardchrbshm65jjtx3gv6yy