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Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors
The Twelfth International Symposium on High-Performance Computer Architecture, 2006.
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single application is critical in light of the expanding performance demands of important future workloads. This work addresses the problem of dynamically optimizing power consumption of a parallel application that executes on a many-core CMP under a given performance constraint. The optimization space is twodimensional,
doi:10.1109/hpca.2006.1598114
dblp:conf/hpca/LiM06
fatcat:6hnet6w3wbhnvgo3ghzvl7uy3a