K. H. Tsai, S. Hellebrand, J. Rajski, M. Marek-Sadowska
1997 Proceedings of the 34th annual conference on Design automation conference - DAC '97  
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order and polarity in scan synthesis, effectively converting the scan chain into a ROM capable of storing some "center" patterns from which the other vectors are derived by randomly complementing some of their coordinates. Experimental results demonstrate that a very high fault coverage can be obtained without any
more » ... on of the mission logic, no test data to store and very simple BIST hardware which does not depend on the size of the circuit.
doi:10.1145/266021.266203 dblp:conf/dac/TsaiHRM97 fatcat:whptwcv32zff3aikdvvrgjf44a