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Worst-Case Execution Time Analysis of Predicated Architectures
2017
Worst-Case Execution Time Analysis
The time-predictable design of computer architectures for the use in (hard) real-time systems is becoming more and more important, due to the increasing complexity of modern computer architectures. The design of predictable processor pipelines recently received considerable attention. The goal here is to find a trade-off between predictability and computing power. Branches and jumps are particularly problematic for high-performance processors. For one, branches are executed late in the
doi:10.4230/oasics.wcet.2017.6
dblp:conf/wcet/BrandnerN17
fatcat:jm2njv7b7zdjfoshidhpm2s7f4