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Novel Modulo 2^n + 1 Multipliers
2006
9th EUROMICRO Conference on Digital System Design (DSD'06)
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A new modulo 2 n + 1 multiplier architecture is proposed for operands in the normal representation. The novel architecture is derived by showing that all required correction factors can be merged into a single constant one and by treating this, partly as a partial product and partly by the final parallel adder. The proposed architecture utilizes a total of (n + 1) partial products, each n bits wide and is built using an inverted end-around-carry, carry-save adder tree and a final parallel adder. *
doi:10.1109/dsd.2006.71
dblp:conf/dsd/VergosE06
fatcat:wnhpbyza3nhstn3wwd3vkm3yge