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Fault-tolerant resynthesis with dual-output LUTs
2010
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)
We present a fault-tolerant post-mapping resynthesis for FPGA-based designs that exploits the dual-output feature of modern FPGA architectures to improve reliability of a mapped circuit against faults. Emerging FPGA architectures, such as 6-LUTs in Xilinx Virtex-5 and 8-input ALMs in Altera Stratix-III, have a secondary LUT output that allows access to non-occupied SRAM bits. We show that this architectural feature can be used to build redundancy for fault masking with limited area, power, and
doi:10.1109/aspdac.2010.5419873
dblp:conf/aspdac/LeeHMHL10
fatcat:hgquubo63rgqnhfipv6fvbgjlu