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Full-chip multilevel routing for power and signal integrity
2007
Integration
Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wirelimited deep sub-micron designs. In this paper, we present a novel design methodology that simultaneously considers global signal routing and power network design under integrity constraints. The key part to this approach is a simple yet accurate power net estimation formula that decides the minimum number of power nets needed to
doi:10.1016/j.vlsi.2005.11.001
fatcat:rlcge4yzqrfxdpvunvw4vk4p2i