In Microprocessor power minimization is a major concern. Many circuit and micro-architectural innovations have been proposed to reduce power in many individual processor units. The strategy is used to dynamically and simultaneously adjust the reorder buffer to reduce power dissipation in the data path without significant impact on the performance. Therefore a challenge is to find a centralized approach which can address power issues for one unit with the least amount of redesign and

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... efforts and the least hardware overhead. Therefore it proposes such a centralized approach that attempts to simultaneously reduce power in processor unit with highest dissipation in reorder buffer. It is based on an observation that utilization varies significantly, during cache miss period. Some of the superscalar processors, such as the Intel processor implement physical registers using the Reorder Buffer (ROB) slots. One of the main dynamic instruction scheduling artifacts used in such datapath designs is the Reorder Buffer (ROB), which is used to recover to a precise state when interrupts or branch mispredictions occur. One of the power reduction technique used in ROB is dynamic resizing. Index Terms: Cache miss driven, centralized low power technique, dynamic resource resizing, SRAM unit.