An 8-bit 250 megasample per second analog-to-digital converter: operation without a sample and hold

B. Peetz, B.D. Hamilton, J. Kang
1986 IEEE Journal of Solid-State Circuits  
A monolithic 8-bit 250 megasarnple per second analog-todigii at converter (ADC) fabricated in an oxide-isolated bipolar process is deseribed. Using a flash ADC architecture at high speeds without a sample and hold leads to a number of error sources discussed in this paper. The design of the converter is optimized to miuimize the effects of these error sources. Experimental results are presented for comparison with theory.
doi:10.1109/jssc.1986.1052641 fatcat:nu2k6hcwqnc6zoz32kv2qtlfqa