A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf
.
Reduction of Test Time using Multiple Test Control Point Insertion for 7nm Technology Node
2020
VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE
Test time reduction is a prominent challenge in scan based Design For Testability (DFT) architectures for cost effective test. Reliability and testability both are main objectives for DFT in today's VLSI design. In this paper, we have proposed multiple standard test control point insertion technique for 7nm technology node. The design was tested on 7828 sequential cells. We have compared results of following three Design Rule Check (DRC) (1) Scan DRC (2) Clock Scan DRC (3) Multiple standard
doi:10.35940/ijitee.e2946.039520
fatcat:274lvhd3yff25fddjy4opgwnza