Optimally-placed twists in global on-chip differential interconnects

E. Mensink, D. Schinkel, E. Klumperink, E. van Tuijl, B. Nauta
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.  
A bus-transceiver test chip in 0.13 µm CMOS achieves 3 Gb/s/ch over 10 mm long uninterrupted differential interconnect of only 0.8 µm pitch. As crosstalk would impede this high data rate, twists are used. Analysis shows that the optimal positions of the twists depend on the termination of the interconnect. Theory and measurements show that only one twist at 50% of the even interconnects, two twists at 30% and 70% of the odd interconnects and equal source and load impedances are very effective in mitigating the crosstalk. 0-7803-9205-
doi:10.1109/esscir.2005.1541663 fatcat:zp2r7op2lvccxpmhtiqn3xucle