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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)
We propose a Virtual Pipelined Memory (VPM) architecture for fast row-cycle by using top-down design approach. A pipeline structure in row path and integration of multiple SRAM buffers enable fast rowcycle. VPM shows higher performance than that of SDRAM by about 40% and that of VCM by about 20%. VPM maintains backward compatibility with conventional SDRAM interface and consumes low power adopting partial cell core activation.doi:10.1109/apasic.1999.824115 fatcat:j76avbhi7faddjqq4hhuglmegi