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Spin-Transfer Torque RAM (STTRAM) is a promising alternative to SRAMs in on-chip caches, due to several advantages, including nonvolatility, low leakage, high integration density, and CMOS compatibility. However, STTRAMs' wide adoption in resource-constrained systems is impeded, in part, by high write energy and latency. A popular approach to mitigating these overheads involves relaxing the STTRAM's retention time, in order to reduce the write latency and energy. However, this approach usuallydoi:10.1145/3299874.3318022 dblp:conf/glvlsi/KuanA19 fatcat:qns6nfurvfcxxkg6r5mrvjbzpq