A 6 K-gate GaAs gate array with a new large-noise-margin SLCF circuit

T. Terada, Y. Ikawa, A. Kameyama, K. Kawakyu, T. Sasaki, Y. Kitaura, K. Ishida, K. Nishihori, N. Toyoda
1987 IEEE Journal of Solid-State Circuits  
A 6K-gate GaAs gate array has been successfully designed and fabricated using a new huge-noise-margin Schottky-diode Level-shifter Capacitor-coupled FET logic (SLCF) circuitry and a WNX-gate self-afigned LDD structure GaAs MESFET process. Chip size was 8.OX 8.0 md. A basic cell can be programmed as an SLCF inverter, a two-inpnt NO& or a two-inpnt NANDgate. The mdoaded propagation delay time was 76 ps/gate at a 1.2-mW/gate power dissipation. The increases in delay time due to various loading
more » ... citances were 10 ps/fan-in, 45 ps\fan-out, and 0.64 ps/fF. A MM seriaf-to-pataflel-to-seriaf (S/P/S) data-conversion circuit was constructed on the gate array as an application example. A maximum operation freqnency of 852 MHz was achieved at a 952-mW power dissipation, including 1/0 buffers.
doi:10.1109/jssc.1987.1052810 fatcat:5w44tp2jargyhmuifycvo3ueya