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A high performance low power dynamic PLA with conditional evaluation scheme
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
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This paper proposes a high performance and low power dynamic CMOS PLA that minimizes active power consumption. The proposed PLA uses a conditional evaluation scheme to reduce short circuit power consumption during the evaluation phase. The proposed PLA reduces delay by 13.8%, dynamic power by 46%, and total power delay product (PDP) by 53.4% compared to the conventional clock-delayed PLA in a 0.25um CMOS process technology.
doi:10.1109/iscas.2004.1329413
fatcat:weht3tkpkbgwrazwu54rwhby2y