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A Generic Multi-Phase On-Chip Traffic Generation Environment
2006
IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)
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We present hereafter a framework for on-chip traffic generation and networks-on-chip performance evaluation. This framework is based on a traffic generator that has three important characteristics: the splitting of traffic generation in multiple phases, the ability to replay a previously recorded trace in various interconnect systems, and the capacity to produce stochastic traffic with advanced statistical properties. We focus here on the second characteristics, by validating it in
doi:10.1109/asap.2006.5
dblp:conf/asap/ScherrerFR06
fatcat:lbnd3zfz5rdsbliojj5d3othkq