A Generic Multi-Phase On-Chip Traffic Generation Environment

Antoine Scherrer, Antoine Fraboulet, Tanguy Risset
2006 IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)  
We present hereafter a framework for on-chip traffic generation and networks-on-chip performance evaluation. This framework is based on a traffic generator that has three important characteristics: the splitting of traffic generation in multiple phases, the ability to replay a previously recorded trace in various interconnect systems, and the capacity to produce stochastic traffic with advanced statistical properties. We focus here on the second characteristics, by validating it in
more » ... e SystemC simulations. * This work has been partly founded by CNRS and ST-Microelectronics † This work has been done during a one year INRIA delegation in the COMPSYS group at ENS Lyon
doi:10.1109/asap.2006.5 dblp:conf/asap/ScherrerFR06 fatcat:lbnd3zfz5rdsbliojj5d3othkq