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As technology feature geometries shrink, failures caused by signal integrity issues have become prominent during test. To avoid the time consuming silicon inspection and reduce the engineering cost and effort for failure analysis, a fast and cost-effective diagnostic flow is proposed in this paper. The flow targets delay faults and can be used to (1) identify noise-related failures with a quiet pattern and (2) evaluate the failed pattern in terms of its noise-induced delay to help identify thedoi:10.1109/vts.2011.5783739 dblp:conf/vts/MaAT11 fatcat:aniyuxek7raepf2ht3vqw73r6u