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IFIP Advances in Information and Communication Technology
Modern multiprocessors are equipped with local caches, to enhance program performance. However, the presence of caches can lead to the violation of sequential consistency  assumptions regarding program order and write atomicity. With respect to such relaxed memory models , we provide an operational description of program execution (in the style of ) that accounts for cache effects. In particular, we provide an operational characterization of cache invalidation and update policies anddoi:10.1007/978-3-642-15240-5_27 fatcat:pgv2kq4wtjgpfb4q4qqiau3mje