A design methodology for domain-optimized power-efficient supercomputing

Marghoob Mohiyuddin, Mark Murphy, Leonid Oliker, John Shalf, John Wawrzynek, Samuel Williams
2009 Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis - SC '09  
As power has become the pre-eminent design constraint for future HPC systems, computational efficiency is being emphasized over simply peak performance. Recently, static benchmark codes have been used to find a power efficient architecture. Unfortunately, because compilers generate sub-optimal code, benchmark performance can be a poor indicator of the performance potential of architecture design points. Therefore, we present hardware/software co-tuning as a novel approach for system design, in
more » ... hich traditional architecture space exploration is tightly coupled with software auto-tuning for delivering substantial improvements in area and power efficiency. We demonstrate the proposed methodology by exploring the parameter space of a Tensilica-based multiprocessor running three of the most heavily used kernels in scientific computing, each with widely varying micro-architectural requirements: sparse matrix vector multiplication, stencil-based computations, and general matrix-matrix multiplication. Results demonstrate that co-tuning significantly improves hardware area and energy efficiency -a key driver for next generation of HPC system design. Generate new code variant Generate new HW config.
doi:10.1145/1654059.1654072 dblp:conf/sc/MohiyuddinMOSWW09 fatcat:rzk52sgxqbdubov2r3oon6r32u