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A design methodology for domain-optimized power-efficient supercomputing
2009
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis - SC '09
As power has become the pre-eminent design constraint for future HPC systems, computational efficiency is being emphasized over simply peak performance. Recently, static benchmark codes have been used to find a power efficient architecture. Unfortunately, because compilers generate sub-optimal code, benchmark performance can be a poor indicator of the performance potential of architecture design points. Therefore, we present hardware/software co-tuning as a novel approach for system design, in
doi:10.1145/1654059.1654072
dblp:conf/sc/MohiyuddinMOSWW09
fatcat:rzk52sgxqbdubov2r3oon6r32u