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Since their introduction by Kocher in 1998, power analysis attacks have attracted significant attention within the cryptographic community. While early works in the field mainly threatened the security of smart cards and simple processors, several recent publications have shown the vulnerability of hardware implementations as well. In particular, Field Programmable Gate Arrays are attractive options for hardware implementation of encryption algorithms, but their security against power analysisdoi:10.1109/jproc.2005.862437 fatcat:6idhtqy76nemrbpeesvd4swheq