Simulating clock jitter in digital communication systems

M.G. Makhija, V.P. Telang
Proceedings of ICC/SUPERCOMM '96 - International Conference on Communications  
For reliable digital communication between devices, the sources that contribute to data sampling errors must be properly modeled and understood. Clock jitter is one such error source occurring during data transfer between integrated circuits. Clock jitter is a noise source in a communication link similar to electrical noise, but is a time domain noise variable affecting many different parts of the sampling process. Presented in this dissertation, the clock jitter effect on sampling is modeled
more » ... mpling is modeled for communication systems with the degree of accuracy needed for modern high speed data communication. The models developed and presented here have been used to develop the clocking specifications and silicon budgets for industry standards such as PCI Express, USB3.0, GDDR5 Memory, and HBM Memory interfaces. ii ACKNOWLEDGEMENTS My thanks and best wishes goes to my Portland State advisors and friends, Dr. Solanki, Dr. Leung, and Dr. Rice, for their years of support and encouragement in my educational endeavors. This work has been made possible by the support of my management, my colleagues, and friends at Intel Corporation over the last 22 years. In particular, I owe a debt of gratitude to
doi:10.1109/icc.1996.541275 fatcat:2irjiyhgrndufbcihgno4rgpre