Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices

Mohammad Hosseinabady, Jose Luis Nunez-Yanez
2015 2015 25th International Conference on Field Programmable Logic and Applications (FPL)  
This paper presents a workgroup synthesis mechanism to compile an OpenCL kernel to FPGA-based accelerators embedded in a multi-core CPU system-on-a-chip (SoC). The OpenCL kernels considered in this paper exhibit regular data access patterns. Coping with the limited amount of internal memory in embedded FPGAs, the workgroup synthesis utilises a novel data access pattern formulation to describe the parallelism already provided by the OpenCL kernels. To provide an OpenCL framework prototype to
more » ... date the proposed technique, a source-to-source compiler that transforms the OpenCL kernel into C/C++ code is developed. Then vendor-specific high-level synthesis tools are used to convert the C/C++ code into the FPGA bitstream. Results based on popular real applications show up to 89.8% improvement in the execution time compared to the commercial FPGA OpenCL implementations.
doi:10.1109/fpl.2015.7294016 dblp:conf/fpl/HosseinabadyN15a fatcat:mrl6eey55rdmbiwepgi7xscgfi