Voltage controlled sub-THz detection with gated planar asymmetric nanochannels

H. Sánchez-Martín, J. Mateos, J. A. Novoa, J. A. Delgado-Notario, Y. M. Meziani, S. Pérez, H. Theveneau, G. Ducournau, C. Gaquière, T. González, I. Íñiguez-de-la-Torre
2018 Applied Physics Letters  
This letter reports on room temperature sub-THz detection using self-switching diodes based on an AlGaN/GaN heterostructure on a Si substrate. By means of free-space measurements at 300 GHz, we demonstrate that the responsivity and noise equivalent power (NEP) of sub-THz detectors based on planar asymmetric nanochannels can be improved and voltage controlled by means of a top gate electrode. A simple quasi-static model based on the DC measurements of the current-voltage curves is able to
more » ... the role of the gate bias in its performance. The best values of voltage responsivity and NEP are achieved when the gate bias approaches the threshold voltage, around 600 V/W and 50 pW/Hz 1/2 , respectively. A good agreement is found between modeled results and those obtained from RF measurements under probes at low frequency (900 MHz) and in free-space at 300 GHz. Published by AIP Publishing. https://doi.org/10.1063/1.5041507 In the last few years, different THz detectors have been investigated, looking for larger bandwidth and lower noise, with increasing practical interest in security, medical imaging, and high speed short range communications, among other fields. 1 A non-classic architecture based on a single nanolithography step allowing to define an asymmetric planar diode so-called Self-Switching diode (SSD) was proposed by Song in 2003. 2 This particular geometry propagates the applied bias into a lateral field effect, which depending on the polarity is able to open or close the channel because of electrostatic and surface effects. 3 The use of high mobility materials like InGaAs, 4 InAs, 5 or graphene 6 for fabricating SSDs has allowed envisaging its use in relevant THz applications such as zero-bias detectors for passive imaging. In addition, GaN despite its lower mobility is also suitable for sub-THz detection. 7 In all the cases, reducing the channel width is the first strategy to enhance the performance of SSDs as detectors. 8 However, this has a drawback: the variability on their performance. It is difficult to precisely control such a stringent fabrication process and reproducibly fabricate SSDs with channel widths below 100 nm. Moreover, the detection performance depends on the nonlinearity of the I-V curve of the SSDs, which critically depends on the presence of surface charges at the sidewalls of the channels, so that many unknown trap mechanisms, especially in the GaN technology, arise. 9 In order to control the conductance of planar nanochannels, different solutions based on the field effect have been proposed: (i) in-plane gates, where the confining electric field is parallel to the two-dimensional electron gas (2DEG), 10-13 which provide the transistor effect and voltage-tunability of their I-V curves or (ii) top Schottky contact (SC) gates, 14 used not only in FETs but also in countless semiconductor devices including ballistic devices 15 and Gunn diodes. 16 In this work, we explore the benefits on the main figures of merit of RF detectors, i.e., responsivity (b) and noise equivalent power (NEP), of adding a SC gate on the top of SSDs fabricated on GaN, as sketched in Fig. 1(a) . The conventional vertical field effect mechanism for gating the carrier density in these devices, which we will call gated-SSDs (G-SSDs), will be studied. The advantage of G-SSDs over standard FETs, also showing a nonlinearity in the drain current vs. drain-to-source voltage curves (I D -V DS ) originated from the gate electrode, is that the responsivity of G-SSDs has an additional contribution coming from the lateral field effect (associated with the SSD shape), superimposed to the effect of the top gate. The characterized G-SSDs are based in an AlGaN/GaN heterojunction on a Si substrate grown by EpiGaN consisting of a 25 nm thick AlGaN barrier (with 35% Al content) on top of a 1.5 lm thick GaN buffer. The fabrication process is similar to that of the recess technology presented in Ref. 8, in which, after the dry etching of the trenches, a final step associated with the top gate fabrication is added. This step is done as following: e beam writing of the PMMA and Argon FIG. 1. (a) Sketch of a G-SSD and (b) SEM view of an array of 4 GaN SSDs with a top gate. The position of the source (S, at the left), drain (D, at the right), and gate (G, on the center of the channels) electrodes is also indicated. a)
doi:10.1063/1.5041507 fatcat:pr6jaec43nenhgsahu3ifrvkra