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Post-silicon debugging of a system on chip (SOC) is complex due to (1) the intrinsic limits on the internal observability, (2) the absence of a single global clock, and (3) the need for asynchronous intellectual property (IP) blocks to interact with each other. These aspects prevent the instantaneous capture of a complete and consistent state of the SOC, and make the SOC nondeterministic at both the clock cycle level and the behavioral level. To debug an embedded system when the states that aredoi:10.1109/hldvt.2010.5496668 dblp:conf/hldvt/VermeulenG10 fatcat:hkaj67cg2be4fo36vota2gy7pm