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An Energy Efficient Instruction Window for Scalable Processor Architecture
2008
IEICE transactions on electronics
Modern microprocessors achieve high application performance at the acceptable level of power dissipation. In terms of power to performance trade-off, the instruction window is particularly important. This is because enlarging the window size achieves high performance but naive scaling of the conventional instruction window can severely increase the complexity and power consumption. In this paper, we propose lowpower instruction window techniques for contemporary microprocessors. First, the
doi:10.1093/ietele/e91-c.9.1427
fatcat:2f63nye4kzct7hdx536a4jb3ki