Rigorous Design of 22-nm Node 4-Terminal SOI FinFETs for Reliable Low Standby Power Operation with Semi-empirical Parameters

Seong-Jae Cho, Shinichi O'uchi, Kazuhiko Endo, Sang-Wan Kim, Young-Hwan Son, In-Man Kang, Meishoku Masahara, James S.Jr Harris, Byung-Gook Park
2010 JSTS Journal of Semiconductor Technology and Science  
In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band
more » ... ling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation. Index Terms-Device design, gate-induced drain leakage (GIDL), fin-shaped field-effect transistor (FinFET), TCAD simulation, carrier lifetime, bandto-band tunneling (BTBT), underlap length Manuscript
doi:10.5573/jsts.2010.10.4.265 fatcat:puyg7uqlmbhfxgesfk5eiqvqoa