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Lecture Notes in Computer Science
Minimizing power consumption continues to grow as a critical design issue for many platforms, from embedded systems to CMPs to ultrascale parallel systems. As growing cache sizes consume larger portions of the die, reducing their power consumption becomes increasingly important. Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Partitioning reduces dynamic power via smaller, specialized structures. We introduce a reuse distance (RD) drowsy caching mechanismdoi:10.1007/978-3-642-00904-4_5 fatcat:o2do5vhuarh3na2kjnv6h2pvm4