A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2012; you can also visit the original URL.
The file type is application/pdf
.
Worst-case response time analysis of resource access models in multi-core systems
2010
Proceedings of the 47th Design Automation Conference on - DAC '10
Multi-processor and multi-core systems are becoming increasingly important in time critical systems. Shared resources, such as shared memory or communication buses are used to share data and read sensors. We consider realtime tasks constituted by superblocks, which can be executed sequentially or by a time triggered static schedule. Three models to access shared resources are explored: (1) the dedicated access model, in which accesses happen only in dedicated phases, (2) the general access
doi:10.1145/1837274.1837359
dblp:conf/dac/SchranzhoferPCTC10
fatcat:b4qxrakt6nbixmafazcltmgpam