Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization [chapter]

Avinash Lingamneni, Christian Enz, Krishna Palem, Christian Piguet
2011 Lecture Notes in Computer Science  
Contrary to the existing techniques to realize inexact circuits that relied mostly on scaling of supply voltage or pruning of "leastsignificant" components in conventional correct circuits to achieve cost (energy, delay and/or area) and accuracy tradeoffs, we propose a novel technique called Probabilistic Logic Minimization which relies on synthesizing an inexact circuit in the first place resulting in zero hardware overhead. Extensive simulations of the datapath elements designed using the
more » ... osed technique demonstrate that normalized gains as high as 2X-9.5X in the Energy-Delay-Area product can be obtained when compared to the corresponding correct designs, with a relative error magnitude percentage as low as 0.001% upto 1%.
doi:10.1007/978-3-642-24154-3_21 fatcat:swzrk2burrfpjglha5rzvgf4tu