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Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization
[chapter]
2011
Lecture Notes in Computer Science
Contrary to the existing techniques to realize inexact circuits that relied mostly on scaling of supply voltage or pruning of "leastsignificant" components in conventional correct circuits to achieve cost (energy, delay and/or area) and accuracy tradeoffs, we propose a novel technique called Probabilistic Logic Minimization which relies on synthesizing an inexact circuit in the first place resulting in zero hardware overhead. Extensive simulations of the datapath elements designed using the
doi:10.1007/978-3-642-24154-3_21
fatcat:swzrk2burrfpjglha5rzvgf4tu