A pipelined architecture for ray/bezier patch intersection computation

R.R. Lewis, Renwei Wang, D. Hung
<span title="">2003</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qbxati26c5azbokfsk2tkrbeli" style="color: black;">Canadian journal of electrical and computer engineering</a> </i> &nbsp;
We describe an algorithm for computing ray/Bézier patch intersections from a hardware design aspect. This algorithm uses patch subdivision and other geometrical techniques to find a given maximum number of intersection points nearest to the ray origin. We propose a pipeline-based hardware architecture, verify the number of pipeline stages required by simulation, and estimate the performance of a load-balanced implementation based on a state-of-the-art digital signal processor (DSP).
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/cjece.2003.1426071">doi:10.1109/cjece.2003.1426071</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/5xfiqh5jnba3nbsj46qmhhvtra">fatcat:5xfiqh5jnba3nbsj46qmhhvtra</a> </span>
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