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Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping
2006
IEICE transactions on electronics
A low-power FPGA design approach is proposed based on a fine-grain V DD control scheme called micro-V DD -hopping. Four configurable logic blocks (CLBs) are grouped into one block where V DD is shared. In the micro-V DD -hopping scheme, V DD in each block is changed between V DDH (high V DD ) and V DDL (low V DD ) spatially and temporally in order to achieve lower power without performance degraded. A low-power level shifter that has less contention is also proposed for lowswing inter-block
doi:10.1093/ietele/e89-c.3.280
fatcat:7rnccessrff7ta3psclq7skeau