Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping

C. Q. TRAN
2006 IEICE transactions on electronics  
A low-power FPGA design approach is proposed based on a fine-grain V DD control scheme called micro-V DD -hopping. Four configurable logic blocks (CLBs) are grouped into one block where V DD is shared. In the micro-V DD -hopping scheme, V DD in each block is changed between V DDH (high V DD ) and V DDL (low V DD ) spatially and temporally in order to achieve lower power without performance degraded. A low-power level shifter that has less contention is also proposed for lowswing inter-block
more » ... als. The FPGA incorporates the Zigzag power-gating scheme, in which special care has been taken to cope with a sneak leakagepath problem. A test chip was fabricated using a 0.35-µm CMOS technology, together with the conventional fixed-V DD FPGA for comparison. Measurement results show that dynamic power in the proposed scheme can be reduced by 86% when a frequency is half of the maximum one. Simulation using a 90-nm CMOS technology shows that leakage power can be reduced by 97%, when the proposed method is used. The area overhead of the proposed FPGA is 2%.
doi:10.1093/ietele/e89-c.3.280 fatcat:7rnccessrff7ta3psclq7skeau