Low temperature silicon circuit layering for three-dimensional integration

S.K. Kim, L. Xue, S. Tiwari
2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573)  
We report a thin device layer (~1µm) transfer technique that allows wafer scale transplanting of fully fabricated circuits of SOI on to a host substrate to produce 3-D integrated circuits. This 3-D Parallel Layering Process (3-D PLP) uses temperature below 330 C and incorporates BCB as the dielectric bonding layer. The technique is particularly suitable for 3-D mixed-signal or heterogeneous integration applications where digital and RF/analog circuits benefit from separate manufacturing. Device
more » ... layer to layer alignment of 3 µm is demonstrated. Electrical measurement of the transistors on the SOI donor wafer before and after transfer process is presented.
doi:10.1109/soi.2004.1391589 fatcat:x2exxwurenecdgxbuzd4nehpei