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On-Chip Test Circuit for Measuring Substrate and Line-to-Line Coupling Noise
2006
IEEE Journal of Solid-State Circuits
An on-chip test circuit has been developed to directly measure substrate and line-to-line coupling noise. This test circuit has been manufactured in a 0.35 m double-well double polysilicon CMOS process and consists of noise generators and switched-capacitor signal processing circuitry. On-chip analog-to-digital conversion and calibration are used to eliminate off-chip noise and to extend the measurement accuracy by removing system noise. A scan circuit is described that enables the noise
doi:10.1109/jssc.2005.862349
fatcat:ulxz4ss26zgrpku554ayowg5su