On-Chip Test Circuit for Measuring Substrate and Line-to-Line Coupling Noise

W. Xu, E.G. Friedman
2006 IEEE Journal of Solid-State Circuits  
An on-chip test circuit has been developed to directly measure substrate and line-to-line coupling noise. This test circuit has been manufactured in a 0.35 m double-well double polysilicon CMOS process and consists of noise generators and switched-capacitor signal processing circuitry. On-chip analog-to-digital conversion and calibration are used to eliminate off-chip noise and to extend the measurement accuracy by removing system noise. A scan circuit is described that enables the noise
more » ... m to be reconstructed. On-chip generators ranging in area from 0.25 m 2 to 1.5 m 2 produce noise at the receiver decreasing from 3.14 mV/ m to 0.73 mV/ m. Open and closed guard rings reduce the noise by 20% and 85%, respectively. Measurement of test circuits manufactured with an epitaxial process-5.5m-thick epitaxy with 20 cm resistivity on top of a 120 m bulk with 0.03 cm-exhibits a frequency limit of 50 MHz below which coupling is insensitive to substrate noise. The difference between experimental results and an analytic model of the line-to-line coupling capacitance ranges from 8.5% to 17.7% for different metal layers.
doi:10.1109/jssc.2005.862349 fatcat:ulxz4ss26zgrpku554ayowg5su