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Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks
2015
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
We propose a low-power content-addressable memory (CAM) employing a new algorithm for associativity between the input tag and the corresponding address of the output data. The proposed architecture is based on a recently developed sparse clustered network using binary connections that on-average eliminates most of the parallel comparisons performed during a search. Therefore, the dynamic energy consumption of the proposed design is significantly lower compared with that of a conventional
doi:10.1109/tvlsi.2014.2316733
fatcat:i3zdsmqedranlg4yaaoixq3gsq