Low Transition LFSR for BIST-Based Applications

M. Tehranipoor, M. Nourani, N. Ahmed
2005 14th Asian Test Symposium (ATS'05)  
This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within random test pattern and between consecutive patterns. In other words, transitions are reduced in two dimensions, i.e. between consecutive patterns (fed to a combinational circuit) and consecutive bits (sent to a scan chain). LT-LFSR is independent of circuit under test and flexible to be used for both BIST and scan-based BIST
more » ... chitectures. The experimental results for ISCAS'85 and '89 benchmarks, confirm up to 77% and 49% reduction in average and peak power, respectively.
doi:10.1109/ats.2005.77 dblp:conf/ats/TehranipoorNA05 fatcat:bfrwccgejvactkks65socxaauu